Role
Student, Apr. 2018
Prototyped and programmed a superscalar, Alpha64-ISA, out-of-order processor with hardware prefetching, advanced branch prediction, and cache enhancements, including non-blocking accesses and a victim cache.
The design process was a time-intensive two months for our five team members, during which we spent time creating modules, unit testing, and integrating them into the final pipeline. The source code, due to the University of Michigan Engineering Honor Code, is not available to the public; however, a detailed report of the processor’s features is below.